1. Field of the Invention
The present invention relates to a static random access memory (SRAM), and particularly relates to a SRAM that keeps the memory cell array under a low voltage in the Standby mode and Write mode, and raises the memory cell array supply voltage to a high voltage in the Read mode.
2. Description of the Prior Art
FIG. 1 is a circuit diagram illustrating a related prior art 6T SRAM static random access memory structure. As shown in FIG. 1, the 6T SRAM structure has a plurality of memory cell circuits, but only two memory cell circuits 101, 103 are symbolized for explaining. For a 6T SRAM cell during Read operation (FIG. 2), a Read disturb voltage is generated at the cell “0” storage node (NT in FIG. 2) when the WL is selected due to the voltage dividing effect between the access (pass-transistor) NMOS and pull-down NMOS. This Read disturb voltage degrades the Read Static Noise Margin (herein after RSNM) and may cause cell stability failures to limit the Read Vmin (Minimum operating voltage). If the Read disturb voltage is higher than the trip voltage of the opposite cell inverter, the cell may flip. During Read/Write operation, the half-selected cells on the selected WL perform dummy Read operation, thus experiencing “Half-Select disturb” similar to the Read disturb of selected cells as shown in FIG. 1.
In Standby mode, the supply voltage of the memory cell array can be lowered to reduce power consumption. In Read mode, the supply voltage of the memory cell array needs to be raised to higher voltage to maintain adequate RSNM and Read performance. In Write mode, to facilitate the writing of data into the memory cell, the supply voltage of the memory cell array should stay low. However, low cell array supply voltage aggravates the “Half-Select disturb”, and the half-selected cells may flip. As a result, the cell array supply voltage for the entire active bank needs to be raised to higher voltage level, thus causing more power consumption.